A Unified Point Multiplication Architecture of Weierstrass, Edward and Huff Elliptic Curves on FPGA

This article presents an area-aware unified hardware accelerator of Weierstrass, Edward, and Huff curves over GF(2233) for the point multiplication step in elliptic curve cryptography (ECC). The target implementation platform is a field-programmable gate array (FPGA). In order to explore design space between processing time various protection levels, this work employs two different algorithms. first Montgomery algorithm Weierstrass Edward curves. second Double Add Binary curve. area complexity reduced by efficiently replacing storage elements that result 1.93 times decrease size memory needed. An efficient Karatsuba modular multiplier implemented compute polynomial multiplications. We utilized square arithmetic unit after execute quad-block variant inversion, which preserves lower resources also reduces clock cycles. Finally, support three curves, controller implemented. Our architecture can operate at maximum 294 MHz utilizes 7423 slices on Virtex-7 FPGA. It takes less computation than most recent state-of-the-art implementations. Thus, combining security (Weierstrass, Huff) single practical applications demand reliability/security levels.